' << ' operator in verilog
Solution 1
<<
is a binary shift, shifting 1 to the left 8 places.
4'b0001 << 1 => 4'b0010
>>
is a binary right shift adding 0's to the MSB.
>>>
is a signed shift which maintains the value of the MSB if the left input is signed.
4'sb1011 >> 1 => 0101
4'sb1011 >>> 1 => 1101
Three ways to indicate left operand is signed:
module shift;
logic [3:0] test1 = 4'b1000;
logic signed [3:0] test2 = 4'b1000;
initial begin
$display("%b", $signed(test1) >>> 1 ); //Explicitly set as signed
$display("%b", test2 >>> 1 ); //Declared as signed type
$display("%b", 4'sb1000 >>> 1 ); //Signed constant
$finish;
end
endmodule
Solution 2
1 << ADDR_WIDTH
means 1 will be shifted 8 bits to the left and will be assigned as the value for RAM_DEPTH
.
In addition, 1 << ADDR_WIDTH
also means 2^ADDR_WIDTH.
Given ADDR_WIDTH = 8
, then 2^8 = 256
and that will be the value for RAM_DEPTH
Solution 3
<<
is the left-shift operator, as it is in many other languages.
Here RAM_DEPTH
will be 1
left-shifted by 8 bits
, which is equivalent to 2^8
, or 256
.
biren.K
Updated on July 18, 2020Comments
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biren.K over 3 years
i have a verilog code in which there is a line as follows:
parameter ADDR_WIDTH = 8 ; parameter RAM_DEPTH = 1 << ADDR_WIDTH;
here what will be stored in
RAM_DEPTH
and what does the<<
operator do here. -
biren.K over 10 yearsThank you .. :) and also thanks for sharing the concept of '>>>' operator.. :)
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Admin over 10 yearsThe >>> operator only preserves the MSB if the shifted operand is signed. If the shifted operand is unsigned, as in your example, the >>> operator inserts zeros just like the >> operator.
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Yvon about 9 years
$signed(test1) >>> 1
is not working for me. Xilinx ISE with ISim. -
Morgan about 9 years@Yvon It should work, unless bug in Xilinx ISE, you could post a question with a code example your trying. otherwise try it out on eda playground.
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Yvon about 9 years@Morgan I pasted your second block of code into ISim, and it says
Syntax error near "signed".
andlogic is an unknown type
. It seems ISim does not recognize those keywords. -
Yvon about 9 years@Morgan Oh I changed
logic
toreg
then all of the three works, giving1100
. -
Morgan about 9 years@Yvon, those are System Verilog keywords, changing file extension to .sv often switches the compiler over.
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Morgan about 9 years@Yvon Signed has been part of verilog for some time, if that is not supported sounds like your stuck with verilog 95 syntax.
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Chandan Choudhury about 2 yearsIf it is register value do we need to assign to same variable
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Morgan about 2 years@ChandanChoudhury any variable can take the shifted value of another, just be careful with the word lengths.