Array of systemverilog interfaces with different inputs

Question

I would like to instantiate an array of systemverilog interfaces where each array element uses a different input.

If all the elements use the same input, then the instantiation is simple:

x_if x_IF[`NUM_INTERFACES](clk);

Here, if `NUM_INTERFACES is 2, then the clk input goes to both x_IF[0] and x_IF[1].

But if I also have

reg clk[`NUM_INTERFACES];

how do I instantiate x_IF so that clk[0] is input to x_IF[0] and clk[1] is input to x_IF[1]?

This is a simple example; I am looking forward to implement this in some sort of loop (probably using generate) for an array of 12 interfaces.

Solution

I would avoid using assign statements, especially with hierarchical references; it makes the code much more difficult to read and maintain.

You could have just done

reg clk[`NUM_INTERFACES];
x_if x_IF[`NUM_INTERFACES](clk);

A feature with arrays of instances is that if the width of a signal being connected to a port is a multiple of the port width, then each instance sill get a slice of the the signal.

See LRM 1800-2012 section 28.3.6 Primitive instance connection list that applies to module ports as well.

If you use a generate loop instead of an array of instances, then I would do

reg  clk[`NUM_INTERFACES];

generate
   for (genvar i=0; i<`NUM_INTERFACES; i++) begin :loop
      x_if x_IF(clk[i]);
   end
endgenerate

Comments

[Kaushal Modi]

Did you mean x_if x_IF[i](clk[i]);? Even then, wouldn't that create multiple interface arrays of incremental lengths up to NUM_INTERFACES? Or does it work because of (clk[i])?

[dave_59]

No I did not mean that. Each iteration of the generate for-loop will create one instance named loop[i].x_IF because the begin block named loop will get elaborated into loop[0], loop[1], etc.

[Kaushal Modi]

Thanks for the explanation. I was unaware of the ability to reference signals using loop[i].

[dave_59]

Note that you can only reference loop[i] if i is a genvar or constant.