Is there a way to tell if my hardware supports specific instructions?

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Per, Ramhound, there is a utility called coreinfo that provides functionality like cat /proc/cpuinfo on Linux.

You have to search through this but you can find the information here,

LAHF-SAHF       -       Supports LAHF/SAHF instructions in 64-bit mode
NX              -       Supports no-execute page protection
CX16            *       Supports CMPXCHG16B instruction
X64             *       Supports 64-bit mode
PREFETCHW       -       Supports PREFETCHW instruction

The - mean that the CPU lacks that feature, the * mean it has that feature.

Now that I look, coreinfo is actually suggested by Microsoft to make the determination on that doc page,

Coreinfo is a tool you can use to confirm which of these capabilities your CPU has.+

Full result for my processor, a Intel E7525, looks like this,

Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright (C) 2008-2014 Mark Russinovich
Sysinternals - www.sysinternals.com

Intel(R) Xeon(TM) CPU 3.40GHz
x86 Family 15 Model 4 Stepping 3, GenuineIntel
Microcode signature: 00000005
HTT             *       Hyperthreading enabled
HYPERVISOR      -       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT

NX              -       Supports no-execute page protection
SMEP            -       Supports Supervisor Mode Execution Prevention
SMAP            -       Supports Supervisor Mode Access Prevention
PAGE1GB         -       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    -       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           -       Supports Supplemental SIMD Extensions 3
SSE4a           -       Supports Streaming SIMDR Extensions 4a
SSE4.1          -       Supports Streaming SIMD Extensions 4.1
SSE4.2          -       Supports Streaming SIMD Extensions 4.2

AES             -       Supports AES extensions
AVX             -       Supports AVX intruction extensions
FMA             -       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           -       Supports XSAVE/XRSTOR instructions
OSXSAVE         -       Supports XSETBV/XGETBV instructions
RDRAND          -       Supports RDRAND instruction
RDSEED          -       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            -       Supports bit manipulation extensions 1
BMI2            -       Supports bit manipulation extensions 2
ADX             -       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            -       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           -       Supports MOVBE instruction
ERMSB           -       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        -       Supports PCLMULDQ instruction
POPCNT          -       Supports POPCNT instruction
LZCNT           -       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       -       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          *       Can write history of 64-bit branch addresses
DS              *       Implements memory-resident debug buffer
DS-CPL          *       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
INVPCID         -       Supports INVPCID instruction
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          -       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
TSC-INVARIANT   -       TSC runs at constant rate
xTPR            *       Supports disabling task priority messages

EIST            *       Supports Enhanced Intel Speedstep
ACPI            *       Implements MSR for power management
TM              *       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          -       Supports x2APIC

CNXT-ID         *       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             *       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       -       Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 00000005 (Basic), 80000008 (Extended).

Logical to Physical Processor Map:
*-  Physical Processor 0
-*  Physical Processor 1

Logical Processor to Socket Map:

Logical Processor to NUMA Node Map:
**  NUMA Node 0

Logical Processor to Cache Map:
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Updated on September 18, 2022

Comments

  • Evan Carroll
    Evan Carroll over 1 year

    Microsoft says, for Windows 2016 Server,

    Minimum:
    1.4 GHz 64-bit processor
    Compatible with x64 instruction set
    Supports NX and DEP
    Supports CMPXCHG16b, LAHF/SAHF, and PrefetchW
    Supports Second Level Address Translation (EPT or NPT)
    1
    

    Is there anyway to find out if say if an

    • HP Workstation xw6200 – Intel E7525 chipset, or a
    • DELL PowerEdge R710 2 x 2.53Ghz E5540

    supports these without manually and exhaustively searching the docs on each chip.

    • Mokubai
      Mokubai over 6 years
    • Evan Carroll
      Evan Carroll over 6 years
      @Ramhound show me on wikipedia where it shows support for PrefetchW
    • Admin
      Admin over 6 years
      @EvanCarroll Read here: en.wikipedia.org/wiki/3DNow!
    • Evan Carroll
      Evan Carroll over 6 years
      @Ramhound according to your own link it says "The two instructions are also available in Bay-Trail Intel processors." That processor was released in 2013. ark.intel.com/products/codename/55844/Bay-Trail
    • Evan Carroll
      Evan Carroll over 6 years
      You haven't shown that Intel supports PREFETCHW prior to 2013. "Wikipedia articles are good sources of information like this." The question is how do I find it? You say Wikipedia. I tell you I looked. You're not showing me anything new.
    • Evan Carroll
      Evan Carroll over 6 years
      How do I know that SSE (Streaming SIMD) includes specifically PREFETCHW?
    • Evan Carroll
      Evan Carroll over 6 years
      According to SSE on Wikpedia, PREFETCHW is not a supported instruction: en.m.wikipedia.org/wiki/Streaming_SIMD_Extensions Only PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA.
    • Evan Carroll
      Evan Carroll over 6 years
      Ok, I only asked because you suggested Wikipedia, but if neither of us know how to find it then I guess it's a good question!
    • Evan Carroll
      Evan Carroll over 6 years
      @Ramhound that's cute you had this conversation before and Peter tried to correct you. Apparently it's not supported in a P4 but the instruction is NOP so windows won't crash on it. That's working outside of their minimal requirements though. Neither the p4 docs nor the Wiki docs talk about support of PREFETCHW on the chip, nor the Intel minimum chip gen that supports PREFETCHW.
    • Evan Carroll
      Evan Carroll over 6 years
      @Ramhound updated
    • Ramhound
      Ramhound over 6 years
      Alright? so we determined that your processors meets the requirements with regards to PREFETCHW since it's a NOP. If this is actual hardware you have you can use coreinfo to determine if the CPU supports the other instructions
    • Evan Carroll
      Evan Carroll over 6 years
      @Ramhound never knew about coreinfo that's most of what I'm looking for you should answer with that. that's like /proc/cpuinfo on *nix.