What is the maximum number of inputs for any logic gate?

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The maximum number of gate inputs is limited due to electrical constraints. It depends on the technology being used.

For example:

A CMOS NAND with three inputs has three transistors connected in series

static CMOS NAND with three inputs

The more inputs, the higher the resistance to draw the NAND output from high to low.

Practical circuit designs strive to either minimize the number of components, the switching latency or the silicon die area.

For a high number of inputs, gates are typically composed of several smaller gates.

Example:
AND5 realized as NAND3 + NAND2 + NOR2

enter image description here

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Updated on June 04, 2022

Comments

  • Admin
    Admin over 1 year

    In the references that we use, I usually see either a 2 or 3-input logic gate. Four-input gates come by once in a while. However, is there a certain limit to the number of inputs a logic gate can have theoretically? I'm assuming in actual practice there is some sort of limit due to the increased complexity as number of input increases. But just hypothetically, are we limited to 4 (because that's the maximum I ever saw in a text by far)? Thanks.

  • user_9
    user_9 almost 3 years
    "The more inputs, the higher the resistance to draw the NAND output from high to low." @Axel Kemper, could you please elaborate on this further? I don't fully understand how this is so. TIA
  • Axel Kemper
    Axel Kemper almost 3 years
    To change output Y from high to low, the three transistors have to conduct electrical current. Their sum of internal resistances determines the time needed to unload the output capacitance. A circuit with three transistors in series needs longer than a circuit with just two transistors. Therefore, the number of inputs has an increasing impact on the latency for a falling edge at the gate output.