Why we cant compare (bne-beq) a register with an immediate (Assembly-MIPS)?

Question

For example on add we have addi for adding a register and an immediate,why on this case we cant have bnei or beqi...

Im supposed to answer on that,but im not sure...any help?

Solution 1

The reason is the instruction encoding:

Both ADDI and BNE/BEQ are I-Type instructions. But whereas the immediate field in the ADDI instruction is used for storing the immediate operand for the addition, it's used for storing the branch offset in the case of BEQ/BNE.

There may be MIPS assemblers which allow you to use immediate operands in conditional branch instructions, but they will expand those pseudo-instructions into multiple actual instructions.

Solution 2

In architectures with flags, the branch instructions usually follow a compare instruction which can compare registers and immediates and set the appropriate flags (often called CMP, but often other instructions can set flags, too). The branch then only checks the flags.

(This was posted before the question was clarified to MIPS, which doesn't use flags)

Comments

[Michael]

Which processor (MIPS?), and which assembler are you using?

[old_timer]

the answer will be in the instruction set documentation, either there is or isnt an instruction for what you are asking. WHY may have to do with bits available for encoding the instruction.

[Thomas]

Yes on MIPS,i forgot to write that.

[Thomas]

Thats the only reason? I think that your answer is what im looking for,but can you explain it a little more? I cant understand this one "it's used for storing the branch offset in the case of BEQ/BNE"

[Michael]

The destination address for BEQ/BNE is not stored as an absolute address, but as an offset relative to the current instruction's location. That offset has to be stored somewhere in the 32-bit instruction word, and that "somewhere" happens to be the immediate field. This is shown on the page I linked to in my answer (the "Conditional branch" row of the integer instruction table).

[Peter Cordes]

But that is how MIPS conditional branch instructions work. If you want to jump farther, you need to get an address into a register and jump to it, or use conditional branches to skip or not-skip a J or JAL instruction which uses more of the instruction bits for a relative offset.

[Peter Cordes]

MIPS doesn't have flags. Its branch instructions take two register operands and do a compare-and-branch for equal or non-equal. Or one register operand to be compared against zero for greater or less than. See this MIPS insn set ref. I guess this was posted before the OP clarified that this was for MIPS. (But what has cmpeq or cmpgt instructions? Most ISAs with flags just have a cmp instruction that sets all flags, then you choose which ones to branch on, with jge or jl or whatever.)

[Photon]

Yes, he clarified later. The cmp** mnemonics are sometimes aliases to generic flag cmp instructions, so that the assembly coder can more easily remember the actual operation. A simple google search shows they are available in multiple ISAs.

[Peter Cordes]

That's not what google is turning up for cmpeq or cmpgt in my searching. Alpha has an actual CMPEQ instruction, which produces a 0 or 1 in a destination register (not flags), so it's like x86's pcmpeqd SIMD instruction, where it's a compare for only one predicate. ARM can conditionally-execute anything, including other CMP instructions, so CMPGT is a conditionally-executed CMP.

[Peter Cordes]

TI C66x has a CMPGT that also produces a 0 or 1, not flags. (like Alpha's CMPEQ). I didn't find any examples of a CMPGT that was just an alias for CMP, and would have allowed a JNE afterwards to branch on a different condition than the one implied by the alias. Can you link what you were finding? I'm curious now, since I'd be surprised if there are any asm syntaxes that work the way you describe, but it's plausible, and I'd be interested to learn something new. Nothing I've found shows a CMPGT just setting flags.

[Photon]

You're right, since this is an old answer, I mixed up the compare and jumps. The compares are actual instructions whereas the jumps had aliases. For example in x86 JE (Jump equal) is another name to JZ (jump on zero flag)

[Peter Cordes]

Ah yeah, that makes sense. x86 has tons of CC synonyms (for Jcc, SETcc, and CMOVcc). It's handy being able to use one that has the right semantic meaning, except when looking at disassembly output which picks one that doesn't match perfectly :P