Assembler error.: Bad instruction

Question

I've run into this error

/tmp/ccK86fyk.s: Assembler messages:
/tmp/ccK86fyk.s:69: Error: bad instruction `sw $3,0(r3)'
/tmp/ccK86fyk.s:70: Error: bad instruction `sw $7,4(r3)'

( The rest of this long code is in this paste.: http://pastebin.com/6YRx8rDh )

The CPU is an arm Cortex-A8 in a project built in maemo fremantle.

So well, I have little assembly knowledge, and I've been studying it and learning a bit more about it, but I can't seem to understand this error. I've also researched thoughout google for a few days now, and I can't find a concrete answer to my problem.

This is the header that has the lines that results in errors.: http://pastebin.com/k3D4cg0d

( Provided more informations on a comment, since I cannot post more than 2 links )

Solution

SW and LW are opcode for MIPS architecture (Load word et Store Word). You can't use this Assembly code with a Cortex A8.

PS: Sorry, I previously said that it was Aarch64 instruction. I was wrong...

Comments

[Luis]

Hum, as I said I have little assembly knowledge, I don't have any definition of 32 or 64 bits compilation. You mean what file I am compiling? it's a bios file from a gba emulator, the gpsp.I also updated my wrong information, it's a arm cortex a8 I am running, I was with my mind on another arm before !

[webshaker]

hum OK.. I understand now... LW and SW do not exist on ARM V7 (and do not exists in aarch64 arm v8 (I've made a mistake)). this is MIPS instruction for Load and Store Word. So this assembly code can't be compiled on a Cortex A8 plateforme. I'll change my post sorry.

[Luis]

I thought this code was already translated, but it seems it still is from the PSP, and psp uses a MIPS processor... How can I make that look ARM friendly?

[webshaker]

I'm not very good to use inline code. If I would try a simple translation, I said that "SW $7, 4(%0)" should be replace by "STR $7, [%0, #4]. I don't know what is %0. propably a address given to the function save_reg. Your have to save $4, $5, $6, ... $14 on ARM (because there less register than on MIPS). LW must be replace by LDR. I hope that help you !

[Luis]

Just after you answered me before, I did some research and discovered about STR and LDR, I changed those, and both my code, and your snipet STR $7, [%0, #4]\n ( On any line ) returns me Error: ARM register expected -- `str $7,[r3,#4], is r3 supported in ARM? Or am I thinking wrong? Also this is the complete C file if anyone would like to take a look.: pastebin.com/5a1jJE1d ( the header file on first post is also complete )

[webshaker]

Yes r3 is a valid register on ARM, but I suppose %0 is a parameter. It could be stored into r0, r1, r2 or r3 ! You must find a doc about inline assembly code.