Does VHDL have a ternary operator?
No. It was discussed for VHDL-2008, but didn't get in. You've got a couple of options. If your tools support VHDL-2008, conditional assignments are now supported as sequential statements (they were previously just concurrent), so you can write something like:
process(clock) begin if rising_edge(clock) then q <= '0' when reset else d; -- ie. much like q <= reset? '0':d; end if; end process;
If you haven't got 2008, just write a function (
q <= sel(reset, '0', d)). You have to write it for every type you're interested in, though.
Not the one like you know from C/C++ but you can use:
destination <= signal1 when condition else signal2;
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user1058795 2 months
I love the neatness of the ternary operator vs if clauses.
Does this operator exist in vhdl? My search was to the contrary. I also checked the when statement out, but it's not an operator, and I want to be able to use it in processes, too...
Dmitri Nesteruk over 6 yearsHow does one add multiple when/else clauses? I cannot seem to get
(cond when x else y) + (cond when z else w)to work.
Ehsan over 2 yearsDon;t use it in Xilinx Vivado. ISIM Simulator doe snot support this construct up to version 2019.2 ! unbelievable.