Makefile: Passing command line arguments to file inside Makefile

Question

Inside my Makfile I have the following,

smktestrun: smktest
    @../projects/test.sh

And I call this using:

Make smktestrun

But sometimes I need to pass an parameter/argument along with this file (test.sh)

So basically I would like:

test.sh -abc

But if i just pass the argument in the Makefile itself, the argument is not taken as simply the sheel script is executed.

So is there a way I could specify in the Makefile that an argument needs to be passed with that file?

Thanks.

Solution

Something like

smktestrun: smktest
        @../projects/test.sh $(TESTARGS)

Then call the Makefile with

$ make smktestrun TESTARGS="-abc"

Comments

[Sunny]

Great thanks.one add-on ?. If i just call: make smktestrun, will it complain that i need the TESTARGS also?

[chepner]

I don't think it should, but if it does, you can just assign a default empty value inside the Makefile with TESTARGS:=