MIPS BNE Instruction
Solution 1
On branch mips executes two instructions -- the branch instruction itself and the one following it (so called branch delay slot).
At the time branch takes effect, PC points to the instruction that follows the branch instruction itself, so -7 is appropriate.
Solution 2
On most architectures, branch targets are calculated from the instruction following the branch instruction (i.e: the PC is already advanced). IIRC ARM is the only common exception (there, the PC has advanced farther still, due to pipelining (of the original ARM implementation)).
darksky
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Updated on June 04, 2022Comments
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darksky almost 2 years
I have a set of instructions as follows:
loop: sll $t1, $t0, 2 # t1 = (i * 4) add $t2, $a0, $t1 # t2 contains address of array[i] sw $t0, 0($t2) # array[i] = i addi $t0, $t0, 1 # i = i+1 add $t4, $t4, $t0 # sum($t4) = ($t4 + array[i]) slt $t3, $t0, $a1 # $t3 = ( i < array_size) bne $t3, $zero, loop # if ( i < array_size ) then loop
The
sll
instruction has an address (program counter) of0x18
.bne
has an address of0x30
. MARS Simulator interprets thebne
instruction as:bne $11, $0, 0xfff9
.0xfff9
is-7
, meaning the instruction will jump 7 steps back. However,sll
is six steps back. Does MIPS take into account the current instruction? Or does this happen because the program counter is incremented in thefetch
stage, before the instruction finishes executing?