Programmatically get the cache line size?

Question

All platforms welcome, please specify the platform for your answer.

A similar question: How to programmatically get the CPU cache page size in C++?

Solution 1

You can use std::hardware_destructive_interference_size since C++17.
Its defined as:

Minimum offset between two objects to avoid false sharing. Guaranteed to be at least alignof(std::max_align_t)

Solution 2

On Linux (with a reasonably recent kernel), you can get this information out of /sys:

/sys/devices/system/cpu/cpu0/cache/

This directory has a subdirectory for each level of cache. Each of those directories contains the following files:

coherency_line_size
level
number_of_sets
physical_line_partition
shared_cpu_list
shared_cpu_map
size
type
ways_of_associativity

This gives you more information about the cache then you'd ever hope to know, including the cacheline size (coherency_line_size) as well as what CPUs share this cache. This is very useful if you are doing multithreaded programming with shared data (you'll get better results if the threads sharing data are also sharing a cache).

Solution 3

On Linux look at sysconf(3).

sysconf (_SC_LEVEL1_DCACHE_LINESIZE)

You can also get it from the command line using getconf:

$ getconf LEVEL1_DCACHE_LINESIZE
64

Solution 4

I have been working on some cache line stuff and needed to write a cross-platform function. I committed it to a github repo at https://github.com/NickStrupat/CacheLineSize, or you can just use the source below. Feel free to do whatever you want with it.

#ifndef GET_CACHE_LINE_SIZE_H_INCLUDED
#define GET_CACHE_LINE_SIZE_H_INCLUDED

// Author: Nick Strupat
// Date: October 29, 2010
// Returns the cache line size (in bytes) of the processor, or 0 on failure

#include <stddef.h>
size_t cache_line_size();

#if defined(__APPLE__)

#include <sys/sysctl.h>
size_t cache_line_size() {
    size_t line_size = 0;
    size_t sizeof_line_size = sizeof(line_size);
    sysctlbyname("hw.cachelinesize", &line_size, &sizeof_line_size, 0, 0);
    return line_size;
}

#elif defined(_WIN32)

#include <stdlib.h>
#include <windows.h>
size_t cache_line_size() {
    size_t line_size = 0;
    DWORD buffer_size = 0;
    DWORD i = 0;
    SYSTEM_LOGICAL_PROCESSOR_INFORMATION * buffer = 0;

    GetLogicalProcessorInformation(0, &buffer_size);
    buffer = (SYSTEM_LOGICAL_PROCESSOR_INFORMATION *)malloc(buffer_size);
    GetLogicalProcessorInformation(&buffer[0], &buffer_size);

    for (i = 0; i != buffer_size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); ++i) {
        if (buffer[i].Relationship == RelationCache && buffer[i].Cache.Level == 1) {
            line_size = buffer[i].Cache.LineSize;
            break;
        }
    }

    free(buffer);
    return line_size;
}

#elif defined(linux)

#include <stdio.h>
size_t cache_line_size() {
    FILE * p = 0;
    p = fopen("/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size", "r");
    unsigned int i = 0;
    if (p) {
        fscanf(p, "%d", &i);
        fclose(p);
    }
    return i;
}

#else
#error Unrecognized platform
#endif

#endif

Solution 5

On x86, you can use the CPUID instruction with function 2 to determine various properties of the cache and the TLB. Parsing the output of function 2 is somewhat complicated, so I'll refer you to section 3.1.3 of the Intel Processor Identification and the CPUID Instruction (PDF).

To get this data from C/C++ code, you'll need to use inline assembly, compiler intrinsics, or call an external assembly function to perform the CPUID instruction.

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Comments

[GManNickG]

FWIW, C++17 will provide a compile-time approximation of this: stackoverflow.com/questions/39680206/…

[haxpor]

aside for C/C++, if you won't mind using assembly to get such info, you can take a look (expanding info from negamartin's answer) at SDL2's source code of SDL_GetCPUCacheLineSize function, then take a look at cpuid macro which has assembly source code for each of processor model. You can take a look at imgur.com/a/KP57m6s, or directly peek at the source yourself.

[oz10]

anyone know about how to do this with other processors with built in cache?

[oz10]

which of the files contains the cache line size? I'm assuming the coherency_line_size? or the physical_line_partition?

[Billy ONeal]

@ceretullis: Errr... the x86 has built in cache. What "other processors" are you specifically looking for? What you're asking for is platform dependent.

[Jakub M.]

To be sure: this is in Bytes, yes?

[John Zwinck]

Yes, coherency_line_size is in bytes.

[hookenz]

Might be better to use sysconf(_SC_LEVEL1_DCACHE_LINESIZE) for linux.

[FrankH.]

simple answers are just the best !

[Alexei Sholik]

Could you post sample values of coherency_line_size as seen on your machines? For those who don't have Linux at hand.

[Abid Rahman K]

@android : I use fedora-18 x64 machine with core-i5 processor. cat /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_siz‌​e returns 64 in my system. Same for index1,2,3 folders also.

[Maarten Bamelis]

@warunapww It is in bytes.

[Elinx]

finally! hope more guys see this answer for time saving.

[Nicholas Humphrey]

Oh my this is really helpful. I'm going to write some game in SDL2 so this is going to be really useful

[Myria]

This technique doesn't work on "Windows Subsystem for Linux", but sysconf(_SC_LEVEL1_DCACHE_LINESIZE) works on WSL.

[user35915]

@Matt why? Just curious :-).

[Frank Liu]

@AbidRahmanK so there is four levels of cache? L0, L1, L2, L3?