VHDL / How to initialize my signal?

Question

I'm a beginner in VHDL and I have a basic question.

Let's consider this following input :

A  : in std_logic_vector(22 downto 0);

And this signal :

signal dummyA : std_logic_vector(47 downto 0);

I want to initialize dummyA with A so what I did is:

dummyA <= A;

Is this correct ? I mean is it equivalent to :

dummyA <= "0000000000000000000000000" & A; ? Or should I add the 0 explicitly like this.

Solution 1

You cannot use dummyA <= A; because there is a type mismatch and any good VHDL compiler will reject it.

You might use something like

dummyA <= (A'RANGE => A, OTHERS => '0');

or (in a sequential context only)

dummyA <= (OTHERS => '0');
dummyA(A'RANGE) <= A;

or

FOR i IN dummyA'RANGE LOOP
    IF i >= A'LOW AND i <= A'HIGH THEN
        dummyA(i) <= A(i);
    ELSE
        dummyA(i) <= '0';
    END IF;
END LOOP;

In a concurrent context you could use

FOR i IN dummyA'RANGE GENERATE
    IF i >= A'LOW AND i <= A'HIGH GENERATE
        dummyA(i) <= A(i);
    END GENERATE;
    -- ELSE
    IF i < A'LOW OR i > A'HIGH GENERATE
        dummyA(i) <= '0';
    END GENERATE;
END GENERATE;

All of the above guarantee that dummyA(i) is loaded with A(i). But "00000" & A could cause mis-pairing, if they ranges don't agree at the low end.

Solution 2

Using a standard function from ieee.numeric_std you can do the following to zero pad the MSBs:

dummyA <= std_logic_vector(resize(unsigned(A), dummyA'length));

---

Although you didn't ask for this, one can also sign-extend like this:

dummyA <= std_logic_vector(resize(signed(A), dummyA'length));

Although I'd argue in that case that the user should be using a signed data-type for both A and dummyA if they are giving them arithmetic interpretations