What does the R stand for in RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP?

Question

The x86 assembler language has had to change as the x86 processor architecture has changed from 8bit to 16bit to 32bit and now 64bit.

I know that in 32bit assembler register names (EAX, EBX, etc.), the E prefix for each of the names stands for Extended meaning the 32bit form of the register rather than the 16bit form (AX, BX, etc.).

What does the R prefix for these register names stand for in 64bit?

Solution 1

I think it's just R for "register", since there are additional registers R8 - R15 on x86-64, and R is a common prefix on many CPU architectures where registers are numbered.

Solution 2

The original Intel x86 processors, the 8080 processor, were 8 bit processors designed with an eye for for applications such as special purpose, small computers (cash registers for instance) or equipment controllers rather than general purpose computers (competitors included the Motorola 6800). The following 8086 processor family (8086 and cost reduced 8088) were 16 bit microprocessors which continued the Intel 8080 architecture while extending it with 16 bit additions with an eye towards more general purpose uses of the processor.

The Intel 8080 and the Intel 8086 processors had a limited number of registers, most of which had special purposes hence they had specific names such as A, B or AX, BX in their assembly language (competitors such as the Motorola 6800 had similar conventions). General purpose computers such as the IBM 360/370 family or the DEC VAX used more generic names for components like registers (e.g. R0, R1, etc.) since the registers were general purpose (Motorola 68000 32 bit processor used in many higher end workstations in the 1980s was similar with eight data registers named D0 through D7).

As Intel has continued evolving the x86 processor over the years since the 1970s, it has also tried to maintain backwards compatibility even as the target applications of the x86 has expanded from specialized, micro-controller applications to general purpose computers. During this evolution, the number of registers has expanded and many of the originally special purpose registers have evolved towards general purpose usage as Intel also introduced the idea of processor chip operating modes with the 80286 to help with backwards compatibility.

With the 64 bit processors, Intel needed some way of identifying a 64 bit transfer versus a 32 bit or other transfer in the assembly language. At the same time Intel was introducing additional, general purpose registers. Using a common industry naming convention for general purpose register, the letter R, followed by a number was an easy decision.

However Intel was also faced with having to maintain backward compatibility for the older registers. So the letter R was used as a prefix to the 16 bit register name just as for 32 bit processors the letter E was used as a prefix to the 16 bit register name. At the same time the design of the 64 bit register operations were done a bit differently than what was done for the 32 bit register operations for previous generations.

With the change from 8 bit processor to 16 bit processor, the registers were extended from 8 bits to 16 bits so the names have the letter X after the register name such as AX, BX, etc. These registers could be treated as two 8 bit registers (16 bit AX register was composed of 8 bit AH and 8 bit AL where the H represents High or most significant bits of the AX register and L represents Low or least significant bits of the AX register).

With the change from 16 bit to 32 bit processor, the registers were extended from 16 bits to 32 bits so the names have the letter E as a prefix such as EAX, EBX, etc. These registers could be treated as having two separate 16 bit components (least significant 16 bits accessed using the 16 bit name such as EAX -> AX, EBX -> BX, etc.) or four 8 bit registers (least significant 16 bits accessed as two 8 bit registers such as EAX -> AH and AL, EBX -> BH and BL, etc.) when register shifting and bitwise operations were used to move 16 bit values between the upper 16 bits and the lower 16 bit of a 32 bit register such as EAX, EBX, etc. This maintained, to some degree, what had been done with the change from 8 bit to 16 bit however direct access to the upper 16 bits of the 32 bit registers was not available the way that direct access to the upper 8 bits of the 16 bit registers in the 8086/8080 had been provided.

Section 3.7.2.1 of Volume 1: Basic Architecture of the Intel 64 and IA-32 Architectures Software Developer's Manual which has this to say about 64 bit mode.

Register operands in 64-bit mode can be any of the following:
• 64-bit general-purpose registers (RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, or R8-R15)
• 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP, or R8D-R15D)
• 16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, BP, or R8W-R15W)
• 8-bit general-purpose registers: AL, BL, CL, DL, SIL, DIL, SPL, BPL, and R8L-R15L are available using REX
prefixes; AL, BL, CL, DL, AH, BH, CH, DH are available without using REX prefixes.
• Segment registers (CS, DS, SS, ES, FS, and GS)
• RFLAGS register
• x87 FPU registers (ST0 through ST7, status word, control word, tag word, data operand pointer, and instruction
pointer)
• MMX registers (MM0 through MM7)
• XMM registers (XMM0 through XMM15) and the MXCSR register
• Control registers (CR0, CR2, CR3, CR4, and CR8) and system table pointer registers (GDTR, LDTR, IDTR, and
task register)
• Debug registers (DR0, DR1, DR2, DR3, DR6, and DR7)
• MSR registers
• RDX:RAX register pair representing a 128-bit operand

See the question and answer for x86_64 registers rax/eax/ax/al overwriting full register contents as well as Why do most x64 instructions zero the upper part of a 32 bit register which provide some explanation about how the 64 bit register operation differ from the 32 bit register operation.

Comments

[Wuschelbeutel Kartoffelhuhn]

Are those registers you mentioned (R8 - R15) 32-bit?

[Wuschelbeutel Kartoffelhuhn]

nevermind i just read that they are all 64 bit so i assume that 32bit emulation will use the same registers with half the spaces 0'd out

[user1568901]

From what I read, 32-bit access to "R" series registers results in the upper 32-bits being automagically zeroed out.

[Peter Cordes]

@Brian: yes, writing any 32bit register (like eax or r11d) zero-extends into the full 64bit register, avoiding the false dependency on old value of the full reg that is a problem with the merging semantics for 16 and 8bit regs.

[Peter Cordes]

AMD designed AMD64 while Intel was committed to IA-64 (Itanium). It wasn't until x86-64 caught on (thanks in part to the high performance of AMD's first AMD64 microarchitecture, K8) that Intel added it to P4 and then P6 (in Core2), calling it "IA-32e".

[Richard Chambers]

@PeterCordes, thanks for that clarification. Reading the brief history in the Intel Software Developer's manual there was mention of of 64 bit first appearing with Intel in a high end version of one of their processors with it becoming available in the next iteration. I am not sure what the difference is between IA-64 Itanium and the P4 and P6. It seems that Itanium was mainly an enterprise server class of processor.

[Peter Cordes]

IA-64 is a totally separate architecture, not x86 at all. P4 is Pentium 4, the "netburst" microarchitecture that was optimized for high clock speed rather than high performance, because at that time CPUs were still marketed by clock speed. P6 is the microarchitecture family started with Pentium Pro/ Pentium II, and culminating in Nehalem. (Sandybridge is a new microarchitecture family.)

[Richard Chambers]

@PeterCordes, thank you for those links. I have some reading to do, especially about Sandybridge.

[Peter Cordes]

Lots of good links in the x86 tag wiki, especially Agner Fog's microarch pdf, which has enough info to predict how many cycles per iteration a loop will run on each of the microarchitectures it covers.

[ci0ccarellia]

This should be the accepted answer

[Mikko Rantalainen]

P4 did indeed have high clock speeds and it was able to also execute the code really fast as long as the code didn't have any branches. It turns out that all normal code is branching all the time and P4 performance was poor.