Who loads the BIOS in RAM during computer bootstrap

boot memory bios operating-systems

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As I wrote in my answer to that question the received folk wisdom on the subject — as unfortunately exemplified by other answers there (and elsehere in SuperUser) — is stuck in the world as it was around 1991, despite the wealth of technical references available explaining how it is now otherwise.

You wouldn't have been this confused if you had read my answer, because you wouldn't be asking about "BIOS loaded from ROM" in the first place.

Your "BIOS chip" is not ROM; there is no machine code between processor startup and the first instruction in firmware; and the "M" in both "RAM" and "ROM" means "memory".

As I wrote before, in modern PCs, the machine firmware is held in non-volatile RAM. It's not ROM as it used to be. See the previous answer for details of the NVRAM chip connected to the LPC bus. (For example: On a machine sitting disassembled beside me as I type this, the NVRAM holding the firmware is a Pm49FL004T, an LPC Flash RAM chip.)

32-bit CPUs don't start up in real mode, and don't start with an address that is below the 1MiB line. That's decades out of date rubbish from the times of 16-bit x86 processors. They start in what is colloquially known as unreal mode, and again in my prior answer I gave the details of what has actually been the case since the advent of the 80386. They load their first instruction from an address that is in fact right at the top of the 32-bit address space, FFFFFFF0.

In my prior answer I told you in detail where the machine firmware is principally mapped into physical address space on 32-bit and 64-bit x86 machines. Remember: Both RAM and ROM are memory. Physical addresses are memory addresses, on the system bus. They can address either RAM or ROM. (They can even address other things as well, but that's just complicating this discussion.) The physical address FFFFFFF0 is 16 bytes below the top of the 512KiB range where the top 512KiB of the firmware, in non-volatile RAM, is always mapped on the system bus by the "chipset".

There's no "loading" from some mythical ROM chip that goes on at processor initialization or reset. The chip holding the firmware is non-volatile RAM. It retains its contents, written when it is "flashed", across power cycles. And the CPU just reads the firmware instructions and data from it, over the system bus and over an LPC bus (and possibly an LPC/FWH bridge) connected to the system bus via the chipset, using a physical memory address.

Cygnus over 1 year

When the computer starts up, the code in BIOS is executed first. However, how is the code in BIOS loaded into the RAM for execution ?

I have referred to this question - Is BIOS read from the BIOS chip or copied into RAM on startup?. However, it has confused me more. If the BIOS is loaded from ROM and the ROM is a separate chip, what is the point of talking about segment addresses in RAM ? Also, where is the BIOS code loaded - is it in the last 1 MiB of real mode address space, or some other location ?

If someone could list the steps from computer start-up upto the execution of first BIOS instruction including the memory addresses used, it would be very helpful
Cygnus over 10 years

Thank you, this seems much more clear to me. However, when you say non-volatile RAM and data being read from it, does it mean that the BIOS is coupled with the RAM in some way ? Does each RAM chip come with a BIOS ? I know this may seem stupid, but I'm a beginner in this topic.
Dougvj over 10 years

When he says non-volatile random access memory (NVRAM) he is referring to a different technology than the RAM used as main system memory (Typically Dynamic Random Access Memory, DRAM). It's a separate chip from main RAM that contains the firmware even when powered off, thus the "non-volatile" part.
Cygnus over 10 years

@Dougvj : In that case, why do we have a separate address of FFFFFFF0 for it ? Wouldn't the NVRAM size be just the size of the firmware ?
JdeBP over 10 years

I think that your questions are better handled as actual questions, not comments on this answer. Look at some of the "Related" questions on the right, then figure out a question to ask that will further your understanding. (There's certainly room on SuperUser for some questions+answers on the very basics, it seems from a brief shufti.)
Sparky_47 over 10 years

@JdeBP I don't know why you insist on calling Pm49FL004T a "Flash RAM chip". It's a serial EEPROM/flash chip like any other, which is page erasable etc, just that it's connected through an LPC bus and not SPI or whatever. There's nothing "RAM-ish" about it. NVRAM is just a genericized term.
Sparky_47 over 10 years

To expand on that point, though. If you interpret the word literally, and not as used commonly, RAM does not contrast ROM. RAM contrasts sequential access memory, like a tape or a CD. In that sense, all modern ROM/flash memories are RAM. But that's not the typical use of the word, since it's convenient to use the term RAM to mean the more narrow meaning, like a computer's "RAM". By the common definition, an EEPROM is not RAM. And the term "flash RAM" is bogus in any case.
Sparky_47 over 10 years

Furthermore, a BIOS/firmware could very well choose to load itself into RAM, for example for performance reasons, or because the code is compressed to save space. But regardless of that, it's indirectly loaded into a type of RAM, namely the cache, and it may also choose to do this explicitly, a technique called cache-as-RAM.
AJMansfield almost 6 years

This is skipping a huge number of steps: you've gotta decode the flash descriptor table, execute the Intel ME to (if nothing else) load microcode, and then somehow map the flash chip BIOS partition - which by the way you don't even know the location of until you've done those other steps - into the expected address range, all before the first opcode of the BIOS can be executed.
JdeBP almost 6 years

No it isn't. You are confused about when all of that happens. It happens after the first instruction is executed. It is, after all, done by the processor executing instructions (in the SEC and PEI phases, roughly). I explained how the firmware code is mapped for the first instruction both in this answer and in the previous one.