How to set all the bits to be 0 in a two-dimensional array in Verilog?
Solution 1
Use a for
loop:
integer i;
always@(posedge clk or posedge reset)
begin
if (reset)
begin
for (i=0; i<8; i=i+1) m[i] <= 2'b00;
end
else
....
end
This is described in the IEEE Std 1800-2012 (Section 12.7.1 The for-loop, for example).
Solution 2
If you can use the current system verilog syntax, then this should work:
always_ff @(posedge clk or posedge reset)
begin
if(reset) begin
m <= '{default:2'b00};
end
else
...
end
See section 5.11 (Array Literals) of the 1800-2012 IEEE standard.
Solution 3
This is actually the one place where for loops are meant to be used.
for (i=0; i<8; i++)
begin
m[i] <= 2'b00;
end
Michael
I'm a firmware engineer and Android development volunteer. I use Verilog, System Verilog, C, C++, Perl, Java, JavaScript, HTML and MATLAB. My interest lies in computer hardware and ASIC design, as well as Android development.
Updated on July 05, 2022Comments
-
Michael almost 2 years
I've built a 8*2bits array to represent a piece of memory in Verilog
reg [1:0] m [0:7]
There is a reset signal for this memory and if reset is 1, all the bits in this memory should be reset to 0. But I don't know how to set all the bits of m in a concise way, because if there are hundreds thousands of bits in the memory, the following way is obviously unfeasible.
always@(posedge clk or posedge reset) begin if (reset) begin m[0]<=2'b00; m[1]<=2'b00; m[2]<=2'b00; m[3]<=2'b00; m[4]<=2'b00; m[5]<=2'b00; m[6]<=2'b00; m[7]<=2'b00; end else .... end
-
Admin over 10 yearsAlthough the memory array you describe will be synthesizable, I'm not sure it is a good idea for "hundreds thousands" of bits. Does your target FPGA/ASIC have some kind of RAM macro cell that would be more efficient?
-
Michael over 10 years@JoeHass I just use "hundreds thousands of bits" as example. I'm working on a design targeting FPGA and that piece of memory contains 2*64 bits at most. But I'm quite curious about your point.What's the meaning of "RAM macro cell"? How could it be more efficient to use "RAM macro cell"? I don't have much experience in FPGA. I appreciate it if you can paraphrase about it. Thanks!
-
-
Michael over 10 yearsThanks, I know this syntax in system verilog. But this syntax is a feature added to the system verilog so it won't work in Verilog
-
nguthrie over 10 yearsJust curious, why can't you use SV? I ask since I have gotten push back in the past on using it for synthesis, but haven't heard a good argument for why.
-
Morgan over 10 years@nguthrie some times a project is tied to using specific version of synthesis tools. It can be part of risk management for the company and not wasting time on every new release. Sometimes the versions people have tied them selves to are quite old.
-
Morgan over 10 yearsNote that the
++
increment operator is only available in SystemVerilog. -
Michael over 10 years@nguthrie Thank you for your suggestion. I'm quite interested in SV but I need to learn it in order to use it. And I have experience using V, so I choose to use V to finish this work. I plan to learn SV recently because I've found SV is very useful in verification, maybe also in design. could you give me some recommendation of tutorials or books? Thanks a lot
-
nguthrie over 10 years@Michael Presentation about useful SV features for design: sutherland-hdl.com/papers/… and the IEEE standard is linked to in my answer
-
Michael over 10 years@nguthrie Thank you so much!