Parameter array in Verilog

Question

Is it possible to create a parameter array in Verilog? For example, anything like the following:

parameter[TOTAL-1 : 0] PARAM_ARRAY = {1, 0, 0, 2}

If it is not possible, what could be the alternative solution?

Solution 1

The given example is assigning unpacked values to packed parameter array. This in not allowed with Verilog.

Verilog only support simple vector based parameters. It does not support unpacked arrays. SystemVerilog, which superseded Verilog, does support parameter arrays. Almost all modern Verilog simulators are really SystemVerilog simulators (at least for the commercial simulators; open source simulators have incomplete support). To have your files read as SystemVerilog, change the file extension for .v to .sv. Then you can assign unpacked to a 2 dimensional parameter array:

parameter [7:0] PARAM_ARRAY [TOTAL-1 : 0]   = {8'd1, 8'd0, 8'd0, 8'd2};

Type names are also allowed. For example, using integer to creates a 32x4 array:

parameter integer PARAM_ARRAY [TOTAL-1 : 0]   = {1, 0, 0, 2};

This is documented in:

• IEEE Std 1364-2001 § 3.11 Parameters
• IEEE Std 1364-2005 § 4.10 Parameters
• (SystemVerilog) IEEE Std 1800-2012 § 6.20 Constants

---

As a pure Verilog solution, you will need to created one long vector:

parameter [8*TOTAL-1:0] PARAM_ARRAY = {8'd1, 8'd0, 8'd0, 8'd2};

Then access with a slice as hard coded PARAM_ARRAY[7:0] or using the +:: PARAM_ARRAY[8*index +: 8]. Note that +: requires Verilog-2001 or higher (which even most open-source simulators support). Indexing vectors and arrays with +:

Solution 2

Verilog doesn't have arrays of parameters, and it doesn't have C-style array initialisation, so you're basically stuck. The two traditional solutions are to combine everything into one big (wide) parameter (and use loops in the 'source' and 'destination' to pack and unpack the wide parameter, in the same way as if you're passing an array through a module port), or to re-think your problem to avoid having to use the array.

You can do it in SystemVerilog, but you didn't ask about that.

Comments

[Chiggs]

Note that because of the ambiguity with the concatenation operator, some tools will require the assignment to be cast: = '{1, 0, 0, 2};

[Prashant]

If using Cadence NCVerilog for simulations, you will need to include the +sv switch when running the simulator from the command line. This is to treat the files containing the parameter definitions as SystemVerilog files

[Greg]

@Prashant That compile argument forces Verilog files to be read as SystemVerilog. It is a bad practice this kind of compile argument. If your project uses legacy Verilog libraries, it may have variable or instance names that are keywords in SystemVerilog. The better approach is to change the file extension on the files you want to be SystemVerilog; from .v to .sv. This is a universal solution, any modern HDL tool (simulator/synthesis/lint/formal/etc.) and syntax highlighter will parse the individual file based on its extension.

[Prashant]

@Greg Thanks for the information. Will follow your advice.

[gwideman]

So far as I can tell, this answer is incorrect. The syntax does not seem to apply to plain Verilog, and the array syntax is not documented in the suggested IEEE Std 1364-2005 section 4.10 Parameter. I copied and pasted Greg's suggested parameter statement into Vivado, and I get "Warning: Concatenation with unsized literal; will interpret as 32 bits. Error: parameter with unpacked dimension is only allowed in SystemVerilog. Error: Cannot assign a packed type to an unpacked type." Adding an apostrophe prefix to the RHS resulted in a syntax error at the apostrophe.

[EML]

@Greg: you need to edit or remove this answer to make it clear that it's SV, not Verilog, which is what this question was tagged as. You reference the 2001 and 2005 LRMs, which are exclusively Verilog, and don't allow this syntax.