Program Counter and Instruction Register

Question

Program counter holds the address of the instruction that should be executed next, while instruction register holds the actual instruction to be executed. wouldn't one of them be enough?

And what is the length of each one of these registers?

Thanks.

Solution 1

You will need both always. The program counter (PC) holds the address of the next instruction to be executed, while the instruction register (IR) holds the encoded instruction. Upon fetching the instruction, the program counter is incremented by one "address value" (to the location of the next instruction). The instruction is then decoded and executed appropriately.

The reason why you need both is because if you only had a program counter and used it for both purposes you would get the following troublesome system:

[Beginning of program execution]

1. PC contains 0x00000000 (say this is start address of program in memory)
2. Encoded instruction is fetched from the memory and placed into PC.
3. The instruction is decoded and executed.
4. Now it is time to move onto the next instruction so we go back to the PC to see what the address of the next instruction is. However, we have a problem because PC's previous address was removed so we have no idea where the next instruction is.

Therefore, we need another register to hold the actual instruction fetched from memory. Once we fetch that memory, we increase PC so that we know where to fetch the next instruction.

P.S. the width of the registers varies depending on the architecture's word size. For example, for a 32-bit processor, the word size is 32-bits. Therefore, the registers on the CPU would be 32 bits. Instruction registers are no different in dimensions. The difference is in the behavior and interpretation. Instructions are encoded in various forms, however, they still occupy a 32-bit register. For example, the Nios II processor from Altera contains 3 different instruction types, each encoded differently. See page 6 of ftp://ftp.altera.com/up/pub/Tutorials/DE2/Computer_Organization/tut_nios2_introduction.pdf

You can learn more about the Nios II processor's structure from the link above as well. It is a simple IP CPU. Of course Intel has their own specification/design and it will vary.

Solution 2

As you stated, the Program Counter (PC) holds the address of the next instruction to execute, and the Instruction Register (IR) stores the actual instruction to be executed (but not its address).

Related to the lenght of these registers, current machines have 64-bit PCs. The length of the IR (from a logical point of view) depends on the architecture:

• RISC machines usually have fixed-length instructions. For example, most SPARC instructions are encoded in 32-bit formats.
• CISC machines (Intel, AMD) have variable-length instructions. For example, see the Intel® 64 and IA-32 Architectures Software Developer Manuals

As these machines are able to fetch, decode and execute several instructions every cycle, the physical implementation of the IR is not easy to describe in a few lines.

Comments

[Peter Cordes]

Or more accurately, there isn't really a physical "instruction register", because code-fetch in modern superscalar (esp. OOO) CPUs happens in large chunks. I don't think I've ever heard the term, and it doesn't get mentioned even in detailed descriptions of how x86 CPUs work internally. (Agner Fog's microarch pdf, or Intel's optimization manual, or other links in the x86 tag wiki. Unless you're actually designing (simple) hardware, it's probably not a useful term for understanding how CPUs work.

[Peter Cordes]

Update: I wrote an answer a while ago on x86 registers: MBR/MDR and instruction registers explaining why x86 doesn't have an "Instruction Register"- it doesn't make sense for a variable-instruction-length ISA that needs complex decoding.