Conditional OR in makefile

Question

I'd like to enable a verbose compilation in my makefile, but I can't figure out how to make a conditional OR.

Let me explain: I want to be able to specify a verbose compilation either by setting V=1 or VERBOSE=1. I want to keep VERBOSE=1 available because we have some scripts that make use of it (and use other makefiles only aware of VERBOSE)

So the result must be that these two commands are the same:

make all VERBOSE=1 # pain to write
make all V=1

Now, my makefile looks like this today:

ifdef VERBOSE
[issue compilation commands with verbose mode]
endif

What I'd like to achieve is close to the preprocessor in C:

if defined(VERBOSE) || defined(V)
[issue compilation commands with verbose mode]
endif

Do you know how to do that?

Solution 1

I do like this:

ifneq "$(or $(LINUX_TARGET),$(OSX_TARGET))" ""

endif

Similar to the $(strip approach, but using the more intuitive $(or keyword

Solution 2

VERBOSE := $(or $(VERBOSE),$(V))

...then...

ifeq ($(VERBOSE),1)
#Conditional stuff
endif

Solution 3

I like Neil Butterworth's approach, but if you really want to do it in the style you describe, this will give you OR:

ifneq "$(strip $(VERBOSE) $(V))" ""
[be verbose]
endif

Comments

[Gui13]

Niiiiice, this one's way clearer. I didn't know about the or.

[villapx]

It does "offer a lot of flexibility"--except that it limits you to using the specific shell that you code it to (in your case, BASH)

[Gui13]

I switched to accept your answer, because it is semantically exactly solving my issue.