Conditional variable define in Makefile with ifeq
22,995
Conditionals can be outside of rules:
ifeq ($(TARGET), android)
$(info Android)
CC=arm-linux-androideabi-gcc
else
$(info native build)
CC=something else
endif
(Note that I've tossed in a few leading spaces, just to make it easier to read-- they are neither necessary nor harmful.)
Author by
user255607
Updated on July 09, 2022Comments
-
user255607 about 2 years
I am trying to define variables in a Makefile, according to conditions. As ifeq can be run only in rules, I have added an additional rule (def_rule) I refer to for each rule.
Example:
def_rule: ifeq ($(TARGET), android) CC=arm-linux-androideabi-gcc else echo "native build" endf all: def_rule tp xi_eid_chipset.o
Unfortunately, invoking make all returns this:
ifeq (linux, android)
/bin/sh: Syntax error: word unexpected (expecting ")")
make: *** [def_rule] Error 2I cannot figure out why. I have just followed examples in GNU Make documentation.
Do you know how to do conditional defines in Makefiles ?