Setting Probes for SimVision in Verilog Code

Question

I am working on simulations of verilog builded digital logic and need to restart a simulation very often to see the changes. I am using Cadence SimVision to review the waveforms.

Is there a way to write commands in verilog for the SimVision environment? I mean things like probes and Parameters.

Solution 1

It is not Verilog but you can create a tcl file.

shm.tcl:

database -open waves -shm
probe -create your_top_level -depth all -all -shm -database waves
run 
exit

Now to run your simulation use:

irun -access +r testcase.sv -input shm.tcl

Solution 2

It's not standard Verilog, but the Cadence tools (ncvlog, ncsim, Incisive) will allow you to set probes from within the Verilog/SV source using a system call.

Check for documentation for $shm_open and $shm_probe.

initial begin
  $shm_open("waves.shm");
  $shm_probe("AS");
end

That said, the answer from @Morgan is the recommended way to do it so that you can control it at runtime.