Verilog input and output array

Question

I am new to verilog, so I was trying this out with it like what I always do in Java, and it just doesn't compile, I tried Googling, but nothing came up ...so, thanks !

module two_to_one_com(SW,LEDR,LEDG);

input [15:0]SW ;
input SW17;
output [7:0]LEDR;
output [7:0]LEDG;

assign X = SW[7:0];
assign Y = SW[15:8];
assign s = SW17;
assign LEDR[7:0] = SW;
assign M = LEDG[7:0];


integer index = 0;
initial
begin
for(index=0;index<=7;index = index+1)
    begin
    assign M[index] = (~s &X[index])|(s&Y[index]);
    end
end


endmodule

So, it just keeps telling me that array M,X and Y can't be indexed as they are undeclared ... Anyone know any solution?

Solution

You need to declare all signals with some type and a width (if greater than 1 bit); assign is not a declaration key word. For example, I use wire:

module two_to_one_com(SW,LEDR,LEDG,SW17);

input [15:0]SW ;
input SW17;
output [7:0]LEDR;
output [7:0]LEDG;

wire [7:0] X = SW[7:0];
wire [7:0] Y = SW[15:8];
wire s = SW17;

Note that I also added SW17 to the port list.

I am still getting complaints about M, but I need to know how wide it should be (# of bits).