Verilog question mark (?) operator

Question

I'm trying to translate a Verilog program into VHDL and have stumbled across a statement where a question mark (?) operator is used in the Verilog program.

The following is the Verilog code;

1  module music(clk, speaker);
2  input clk;
3  output speaker;
4  parameter clkdivider = 25000000/440/2;

5  reg [23:0] tone;
6  always @(posedge clk) tone <= tone+1;

7  reg [14:0] counter;
8  always @(posedge clk) if(counter==0) counter <= (tone[23] ? clkdivider-1 : clkdivider/2-1); else counter <= counter-1;

9  reg speaker;
10  always @(posedge clk) if(counter==0) speaker <= ~speaker;
11  endmodule

I don't understand the 8th line, could anyone please shed some light on this? I've read on the asic-world website that the question mark is the Verilog alternate for the Z character. But I don't understand why it's being used in this context.

Kind regards

Solution 1

That's a ternary operator. It's shorthand for an if statement

Format:

condition ? if true : if false

Example:

tone[23] ? clkdivider-1 : clkdivider/2-1

Translates to something like (not correct syntax but I think you'll get it):

if tone[23] is 1, counter = clkdivider-1
else counter = clkdivider/2-1

Here are two examples of a 2 to 1 MUX using if statement and ternary operator.

On the asic-world website, it is covered under Conditional Operators

Solution 2

Another way of writing, e.g. the following Verilog:

q <= tone[23] ? clkdivider-1 : clkdivider/2-1;

in VHDL would be:

q <= clkdivider-1 when tone[23] else clkdivider/2-1;

Comments

[Admin]

This is why declarations are so essential in questions. A condition must evaluate to a boolean value. The only way tone[23] will meet that criteria is if tone is a BOOLEAN_VECTOR.

[Jim Lewis]

@user1155120 Not so. In VHDL-2008 it is allowed to be a boolean, std_logic, or bit.

[Admin]

The condition operator (9.2.9) which can be applied implicitly (after the when in a conditional assignment statement) is predefined in package standard for type BIT. Absent declarations (or an entity header) the type type of tone is not known. Note the overload condition operator is defined for type std_ulogic in package std_logic_1164 (and would cover elements of the various array types with an element base type of std_ulogic). There's nothing from preventing you providing your own overloaded operator, it converts an element type to a BOOLEAN.

[Admin]

A hurried survey apparently shows no synthesis vendors supporting the condition operator implicit or otherwise.

[Admin]

Oops! shows up in the Synopsys FPGA Synthesis Synplify Pro for Microsemi Edition Reference Manual October 2011. Page 752, both implicit and explict condition operators. There may be earlier references.

[Abhishek Dutt]

Please be more specific.

[DavidYu]

More specific about Mux or the question mark? After knowing it's a MUX it should be enough to translate to VHDL, assuming you understand hardware and vhdl.