VHDL assigning decimal values to std_logic_vector

Question

I'm trying to add a decimal value to a 10 bit std_logic_vector without having to describe every bit. Though it might not be worth the trouble in this particular scenario, i believe it will be very good to know in the future. So far i have:

    signal h_cnt : std_logic_vector(9 downto 0);
    ... --code
    h_cnt <= std_logic_vector(to_unsigned(9, 10));

I get an error message saying:

*Error (10482): VHDL error at vhdl_vga.vhd(70): object "to_unsigned" is used but not declared *

could anyone help me with this one?

Thanks in advance

Solution

I had to replace the libraries i was using.

    use ieee.numeric_std.all;

is what i needed.

Comments

[FarhadA]

Well, you answered the question yourself :)

[Laserbeak43]

loool i forgot that i had answered it, was just curious to see if i had asked a question that had been answered and i hadn't responded to, i saw an answer and was just happy to see it! lol