VHDL difference between => and <=

Question

I keep forgetting and its difficult to search for the answer in a textbook or the Internet.

Solution 1

Well, <= is assignment.

signal <= A or B;

=> is syntax used for case statements like so: (Stolen from http://www.cs.umbc.edu/portal/help/VHDL/sequential.html)

case  my_val  is
  when 1 =>  // This is kind of like how the : operator is used for switch in many languages
    a:=b;
  when 3 =>
    c:=d;
    do_it;
  when others =>
    null; // do nothing
end case;

end case;

=> can also be used in array assignments

myVector <= (1=>'1', OTHERS=>'0');  -- assigns ('0','1','0','0') to "myVector"

Source: http://www.eda.org/comp.lang.vhdl/html3/gloss_example.html

Solution 2

A means to memorize when to use => and when to use <= is to think as follow.

"<=" as an assignment for signal as target (for variable it is ":=" ).

Examples:

y <= a + b + c; --y is a signal
v := a + b +c; --v is a variable

"=>" as mapping.

Example for component explicit mapping (recommended style IMHO):

my_instance : my_component
port map(
  port1 => my_signal1
);

Example for function explicit mapping (useful when parameters are not trivial):

my_signal <= my_function(parameter1 => something1, parameter2 => something2);

Example for array explicit mapping

type array_type is array(0 to 1) of std_logic_vector(7 downto 0);
constant my_array : array_type := (0 => x"AB", 1 => x"CD");

Example for record explicit mapping

type record_type is record
a : natural;
b : std_logic_vector(2 downto 0);
end record;
constant my_record: record_type := (a => 0, b => "101");

The advantage is this style allows you to do the mapping in the order of your choice (not necessarily the order in the definition of the component/function...) . Moreover in the particular case of array with only one item, it is required.

Finally, with the "=>", the keyword others allows to map all the remaining stuff that hasn't already mapped.

Example to assign array :

type array_type is array(0 to 5) of std_logic_vector(7 downto 0);
constant my_array : array_type := (0 => x"AB", 1 => x"CD", others => (others => '0'));

Solution 3

The operator <= is known as a signal assignment operator to highlight its true purpose. The signal assignment operator specifies a relationship between signals. In other words, the signal on the left side of the signal assignment operator is dependent upon the signals on the right side of the operator. (Source: Digital_Mclogic_Design by Bryan Mealy, Section: The Signal Assignment Operator: “<=”, page 339)I couldn't find anything specific on the => operator.

Solution 4

<= represents the assignment operator while => is used in the case statement, for example:

case sel is
  when "01"   => line <= "1";
  when others => line <= "0";
end case

sets line to "1" in case sel is "01" and to "0" otherwise.

=> is also used in structural code in port maps.

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Comments

[Useless Intern]

Hmm that is close to the scenario but I encountered it while working with registers. SHould have stated that first D: ie: others=> (others=>'0')

[Akron]

Are you referring to vector assignments? I updated my answer. When working with vectors, you can use this operator to assign values to specific parts of the vector.