Weak 'H', Pullup on inout bidirectional signal in simulation

Question

Is there a way to tell the simulator (I'm using Modelsim) to pull a signal to weak 'H' when it's not being driven by either bidirectional interface?

For example if I have an I2C signal I2C_SDA that is declared as an inout from 2 modules. One is my actual UUT and the other is a testbench. Both have statements like this:

io_i2c_sda <= r_I2C_DATA when r_I2C_DATA_EN = '1' else 'Z'; 

So both ends are tri-stated. This works fine in simulation, except that the line is BLUE ('Z') all the time that neither end is transmitting. How can I pull-up this line to a 'H' in the code when neither end is transmitting?

Solution

For VHDL, it should be possible to simply add an extra driver to the signal (which has to be of std_logic type), with the constant value 'H'. In Verilog one would use a simple '1' driver and the net type wand for wired and. 'H' specifically means a weak high driver, so it will be overridden by the low drivers.

Comments

[Morten Zilmer]

Yes, in VHDL simply add a continuous assign in the test bench using io_i2c_sda <= 'H'; of type std_logic. The resolution function of std_logic will then result in final signals value of 'H' when the other drivers are 'Z', and '1' if one of the other drivers are '1'.

[Russell]

Wow, I did not know that you could do that. Thanks @MortenZdk. To clarify for anyone else reading this, if you map the two together via a wire, let's call it w_I2C_SDA, you can also assign this wire via a combinational assignment. w_I2C_SDA <= 'H'; Now you have 3 drivers essentially, the UUT, the testbench driver (both of which are high-impedance when not driving) and the test bench combinational assignment w_I2C_SDA <= 'H', and the simulator is able to resolve all 3 of those.

[OllieB]

if you're writing a tristate buffer, you may also want to make use of to_UX01(my_signal), which will perform strength reduction i.e. interpret H and L as '1' and '0' respectively.