concatenate inputs in verilog

Question

In my module I am taking two input 8-bits.

mymodule(input clk, input [7:0] AS_1,input [7:0] AS_2, output [7:0] AS)

Now I want to create a container that will keep both inputs, I mean I want to join them in a single one. I want to do something like that:

reg [15:0] JOIN = AS_1 and AS_2 ---> all their bits should be arranged in a single container

But I don't know whether it should be a reg type or wire or something else, because I'll need to make other operations with that JOIN

Any help, advise or suggestion would be highly appreciated!!!

Solution

It can be reg or wire, you assign them slightly different but the result is the same:

wire [15:0] join;
assign join = {AS_1, AS_2}; //concatenation operator

or:

reg [15:0] join;
always @* begin
    join = {AS_1, AS_2};
end

In either case you can use the value of join exactly the same.

Comments

[bledi]

Is it the same if we could assign like join[15:8]=AS_1; and assign join[7:0]=AS_2; ?

[Morgan]

@bledi you are correct, the same as assign join[15:8]=AS_1; and assign join[7:0]=AS_2;