How to define and assign Verilog 2d Arrays

Question

I'm trying to create a two dimensional array in that form:

reg arr[5:0][0:5];

and when I try to assign a value to it lets say

assign arr[1] = 22;

it gives some errors saying that:

"Reference to scalar reg array 'arr' is not a legal net lvalue" and "Illegal left hand side of continuous assign".

So my intention is to assign a number in the index of the array. How does this assignment work? Any help, suggestion would be highly appreciated.

Solution 1

First of all, you can't assign to regs. assigns drive wire types, not reg types. To drive a reg type you need a statement inside a logic block like an always block.

Secondly, based on what you've written, I think you're looking for an array of multi-bit elements, not a 2d array.

reg arr[5:0][0:5]; Defines a 2D array of single bits. If you want an array of multi-bit values that can hold larger than a bit, you declare it like this:

reg [M:0] arr[0:N] - This describes an array of (N+1) elements, where each element is a M+1 bit number. If you declare it in this fashion, then you should be able to store a value like 22 into it, assuming you use an always block.

Solution 2

You can not use a continuous assignment (aka an assign statement) on a reg type. This has nothing to do with it being an array.

Changing the declaration of arr to be of type wire will get you past the error message you posted. Or, you can assign it using a procedural assignment in an initial or always block.

However you still need to provide both dimensions of the array in the assignment. You are declaring a 2d array of 1-bit values.

So you would need to specify it as:

arr[0][0] = 1;

Comments

[bledi]

Yeah that is exactly what I am looking for. What about storing values, is it a must to use an always block can't we just store them manually? And more thing, should we use assign then?

[Tim]

What do you mean 'manually'? You can use an initial block if you just want to assign it at start of time. assigns are for driving wires only, not regs. Check out any introductory verilog tutorial for more info on the difference between reg and wire.

[EML]

(M+1), (N+1), not -1