System Verilog - case with or

Question

How can I create case with or?

Something like:

string str;

case (str)
   "abc" || "dfg": begin
       //some code
   end
   "yfg": begin
       //some code
   end
   default: //some code
endcase

Solution

You can create a case with OR using a comma like this:

string str;

case (str)
   "abc" , "dfg": begin  
       //some code
   end
   "yfg": begin
       //some code
   end
   default: //some code
endcase

What you're doing is subtly different to ||. You are presenting a list of alternatives to the case statement instead of ORing several expressions together to give one alternative to the case statement.