verilog bit shift with 1

Question

I'm trying to bit shift a value in verilog such that the replaced bits are 1's instead of 0's. i.e. I want to do 0001 << 1 such that it gives 0011 instead of 0010

Solution 1

the command '<<' you use, puts zeros for remaining bits. you can do like the following code:

imagine you have 4 bit variable (like your example) called A.

A = 4'b0000; 
A = {A[2:0], 1'b1};

with concatenation you can put one's instead of zeros.

or you can use 'or' function for this issue:

A = (A << 1) | 4'b0001;

Solution 2

You could do this:

module ones_shift #(log2_width=2) (input [(2**log2_width)-1:0] A,  input [log2_width:0] SHIFT, output [(2**log2_width)-1:0] As);

  wire [(2**log2_width)-1:0] Ai, Ais;

  assign Ai = ~A;
  assign Ais = Ai << SHIFT;
  assign As = ~Ais;

endmodule

ie BITWISE INVERT -> LOGICAL SHIFT LEFT -> BITWISE INVERT

This will work for any valid shift value.

http://www.edaplayground.com/x/YWK

Comments

[BDL]

Although this code might solve the problem, a good answer should also explain what the code does and how it helps.

[Roopa Vikas]

Eg : Lets take the size = 2. Then the first line causes mask_value = 32'hFFFFFFFC. The Second line then inverts this value so you get 32'h00000003 essentially shifting 1s into the mask rather than 0s