VHDL: How to check selected bits of a vector

Question

I'm wondering if there is a way to check only the bits I'm interested in of an std logic vector in VHDL. My newest attempt looks like this:

IF (vectorname = "1-00") THEN

action

END IF;

I am here only interested to check the bits 3, 1 and 0 of the vector. Bit 2 is in this case irrelevant. I thought a - would work since it's "don't care", but it doesn't.

Any ways to do this simply? I know it's possible with STD_MATCH, but I want to take a different approach.

Solution

What's wrong with std_match? That's the "right" way to do it IMHO and I can't immediately think of a reason to "take a different approach"...